1. Field of the Invention
The present invention relates to instruction sets for processors. In particular, the present invention relates to processors having two or more different instruction sets. The present invention also relates to methods of automatically encoding instructions for such processors.
2. Description of the Related Art
A high-performance processor is generally required to have an instruction set which can meet two requirements: compact code (so that the amount of memory required to store the processor's program is desirably small), and a rich set of operations and operands. Such requirements are particularly important in the case of an embedded processor, i.e. a processor embedded in a system such as in a mobile communications device. In this case, high code or instruction density is of critical importance because of the limited resources of the system, for example in terms of available program memory.
However, these two requirements tend to conflict with one another and are difficult to achieve in a single unified instruction set, as compact code involves a minimal encoding for each of the most frequent operations (eliminating the less frequent operations from the instruction set) whereas a rich set of operations and operands requires an orthogonal 32-bit reduced instruction set. Consequently, in a processor having a pre-existing 32-bit instruction set it has been proposed to add a compact 16-bit instruction set which provides the most commonly-used functions and/or access to a limited subset of register operands.
FIG. 1 of the accompanying drawings shows schematically the instruction sets in such a processor. Internally, at the hardware level, the processor has a set of 32-bit instructions ISINT. Externally, the processor has two instruction sets IS1 and IS2. The first instruction set IS1 is made up of the same 32-bit instructions as the internal instruction set ISINT. The second instruction IS2 is made up of 16-bit instructions and the processor contains instruction translation circuitry 200 for translating each 16-bit instruction of the external instruction set IS2 into a corresponding one of the 32-bit instructions of the internal instruction set ISINT.
An embedded processor may also be a very long instruction word (VLIW) processor capable of executing VLIW instructions. The most important additional feature of a VLIW processor is Instruction-Level Parallelism (ISP), i.e. its ability to issue two or more operations simultaneously when executing VLIW instructions.
In such a VLIW processor an instruction issuing unit has a plurality of issue slots, each connected operatively to a different execution unit. It is typical for a VLIW processor that issues two or more instructions per processing cycle to encode each instruction in a different format (or group of formats) depending on the issue slot from which the instruction will be issued. The instructions that will be issued in the same processing cycle are combined together in a VLIW packet or parcel. The position of an instruction in the VLIW parcel determines the sub-set of formats in which that instruction may be encoded. In this way, formats for instructions destined for different positions within the VLIW parcel can use identical encodings without introducing ambiguity.
In practice, empirical observation suggests that 90% or more of the instructions within a program are executed so infrequently that they make up 10% or less of the execution time. Naturally, the remaining 10% of the instructions occupy 90% of the execution time. Furthermore, it is often the case that the infrequently-executed parts of a program will not be able to make effective use of the processor's ability to issue two or more instructions simultaneously. If such parts of the program were encoded using a VLIW instruction set, a large proportion of the instructions would be “no operation” (NOP) instructions inserted in the program by the compiler simply to pad out the VLIW parcels when consecutive instructions cannot appear in the same VLIW parcel because the result of one instruction is used by the next. It follows that, for parts of a program where no effective advantage can be taken of the ability to issue instructions in parallel, or where any performance gain from that ability will have little impact anyway, it is desirable to encode the program to achieve maximum code density (i.e. using the smallest possible number of bits).
Accordingly, it is desirable to provide a VLIW processor with a compact-format instruction set, so as to combine the instruction-level parallelism of VLIW architecture with the compact code “footprint” of a tightly-encoded instruction set such as a 16-bit instruction set.
In the previously-proposed processor discussed above with reference to FIG. 1, the compact instruction set was added after the design of an original 32-bit instruction set, with the result that the translation from the 16-bit instructions into 32-bit instructions is undesirably complex and slow.
It is therefore also desirable to design the instruction-set formats and encodings in such a way that the translation from each external instruction format (e.g. at least one VLIW format, and at least one compact format) into a form that can be executed directly by hardware, can be achieved more efficiently.